The present invention relates to a semiconductor memory device, and more particularly to a power supply circuit for a sense amplifier of a semiconductor memory device.
Semiconductor memory devices, which are used for storage of information, have been advanced toward low costs, miniaturization, and large capacity, in accordance with the technical advances in computer system and electronic communication fields. In particular, the miniaturization of memory chips provides a technical basis for realizing the large capacity.
Generally, a semiconductor memory device such as a DRAM device includes cell blocks each consisting of a number of cells each of which includes one NMOS transistor and one capacitor and which are connected to word lines and bit lines connected in the form of a matrix.
Hereinafter, operation of such a general DRAM device will be described in brief.
When the DRAM device operates, the bit lines of one bit line pair, which have been precharged with a voltage corresponding to ½ of a core voltage Vcore in a standby mode before the operation of the DRAM device, are transited to voltages having a minute voltage difference, respectively, as they receive data from associated cells. When a sense amplifier operates in this state, the voltages of the bit lines, which have a minute difference, are varied to the core voltage Vcore and a ground voltage Vss, respectively. The data on each bit line amplified in the above-mentioned manner is transferred to a data bus line in response to an output signal from a column decoder.
Meanwhile, the time interval between a write command and a precharge command is called a “write recovery time” or “tWR”. The write operation for memory cells should be completed within the write recovery time tWR. In conventional cases, however, there may be a phenomenon that it is impossible to fully pull up data storages to the level of the core voltage VCORE within the write recovery time tWR. This will be described with reference to FIGS. 1 and 2.
Referring to FIG. 1, a semiconductor memory device is illustrated. The semiconductor memory device includes word lines WL0 and WL1, memory cell arrays 120, 180 each including an array of NMOS transistors each connected, at a gate thereof, to an associated one of the word lines WL0 and WL1, and connected, at a drain thereof, to a capacitor, and switches 130, 170 for connecting the memory cell arrays 120, 180 to a sense amplifier 140. The sense amplifier 140, which is also included in the semiconductor memory device, includes PMOS transistors and NMOS transistors. The semiconductor memory device further includes a sense amplifier precharger 150, a YS switch 160 for connecting bit lines BLT0, BLB0 to data lines SIOT and SIOB, respectively, when a command such as a write command WT or a read command RD is input, and a core voltage source 110 for supplying a core voltage VCORE to the sense amplifier 140, as a CSP signal in response to SAP2 signal. SAP2 signal is activated as a high level to conduct a write or read operation. FIG. 2 is a timing diagram of the semiconductor memory device having the above-mentioned configuration.
In each memory cell array of FIG. 1, for example, the memory cell array 120, however, nodes SN0, SN1 thereof functioning as data storages have a relatively high resistance due to the characteristics of the used semiconductor memory fabrication process. Due to such a high resistance, there is a high possibility that the nodes SN0, SN1 cannot be fully pulled up to the VCORE level within a time interval from a write command to a precharge command, namely, the write recovery time tWR. In this case, the word lines may be closed in a state in which data of a level other than the VCORE level, namely, a level of “VCORE-Δ” has been stored in the nodes SN0, SN1. For this reason, there may be a problem of a degradation in the refresh efficiency of the memory cells.